Using design compiler , info about contrainting paths

[always84]

Hi this is the first time i'm using Design Compiler Synopsys tool. I want to optimize my design and so i've to constraint it, after the first analsys of my design, i want to know if constrainting synchronous and asynchoronous paths is usually done and also i'd like to know when I've to put constraint like : input/ouput delay related to clk in synchronous paths, max/min delay in asynchronous paths. Otherwise, if this constraints are usually imposed, how can I estimate their value? Can I estimate them from RTL simulations or are they parameters of flip flops or gates that i've to use during the realization of the chip?

Thanks for helping!

 

[wbpeter]

Always84, did you ever find an answer to this question? I also have the same quetsions regarding timing delay and skew for system-centric and fpga-centric design.

 

[always84]

Hy I solved my problem or better i've understand how to using these constraints. Input and output delay Are calculated with design compiler automatically about the internal wire and ports, the problem is that you want to UsE them For input and output ports of the first level of hierarchy. Usually informations about their values Are realistic in post place & ruote phase, otherwise if the you dont know the values dont put them because the optimization isn't realistic. However you have to set input and output delay only if you want to insert your design in another design and you want to' obtain a realistic timing closure for your design in this New contest. I think these Are all informations that you need.

 

[wbpeter]

Hello Always84,

Can you direct me to some good literature or resources regarding constraining and SDC files you've used to understand this process?

 

[always84]

Ive understand mainly studying both design compiler user guide and reference manual. You can find this manuals easily in the web. If you don't know design compiler is the tool used by Synopsys to make synthesys. The informations about input and output delays were confermed during a lesson about place&route, but about that I haven't any document.