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------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Tue Apr 15 15:45:33 2008 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_DWIDTH -- User logic data bus width
-- C_NUM_CE -- User logic chip enable bus width
-- C_WRFIFO_DWIDTH -- Data width of Write FIFO
-- C_WRFIFO_DEPTH -- Depth of Write FIFO
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus for user logic
-- Bus2IP_BE -- Bus to IP byte enables for user logic
-- Bus2IP_RdCE -- Bus to IP read chip enable for user logic
-- Bus2IP_WrCE -- Bus to IP write chip enable for user logic
-- Bus2IP_RdReq -- Bus to IP read request
-- Bus2IP_WrReq -- Bus to IP write request
-- IP2Bus_Data -- IP to Bus data bus for user logic
-- IP2Bus_Retry -- IP to Bus retry response
-- IP2Bus_Error -- IP to Bus error response
-- IP2Bus_ToutSup -- IP to Bus timeout suppress
-- IP2Bus_Busy -- IP to Bus busy response
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2WFIFO_RdReq -- IP to WFIFO : IP read request
-- IP2WFIFO_RdMark -- IP to WFIFO : mark beginning of packet being read
-- IP2WFIFO_RdRelease -- IP to WFIFO : Return WFIFO to normal FIFO operation
-- IP2WFIFO_RdRestore -- IP to WFIFO : restore the WFIFO to the last packet mark
-- WFIFO2IP_Data -- WFIFO to IP : WFIFO read data
-- WFIFO2IP_RdAck -- WFIFO to IP : WFIFO read acknowledge
-- WFIFO2IP_AlmostEmpty -- WFIFO to IP : WFIFO almost empty
-- WFIFO2IP_Empty -- WFIFO to IP : WFIFO empty
-- WFIFO2IP_Occupancy -- WFIFO to IP : WFIFO occupancy
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_DWIDTH : integer := 64;
C_NUM_CE : integer := 1;
C_WRFIFO_DWIDTH : integer := 64;
C_WRFIFO_DEPTH : integer := 512
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1);
Bus2IP_RdReq : in std_logic;
Bus2IP_WrReq : in std_logic;
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
IP2Bus_Retry : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_ToutSup : out std_logic;
IP2Bus_Busy : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2WFIFO_RdReq : out std_logic;
IP2WFIFO_RdMark : out std_logic;
IP2WFIFO_RdRelease : out std_logic;
IP2WFIFO_RdRestore : out std_logic;
WFIFO2IP_Data : in std_logic_vector(0 to C_WRFIFO_DWIDTH-1);
WFIFO2IP_RdAck : in std_logic;
WFIFO2IP_AlmostEmpty : in std_logic;
WFIFO2IP_Empty : in std_logic;
WFIFO2IP_Occupancy : in std_logic_vector(0 to log2(C_WRFIFO_DEPTH))
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
COMPONENT VGAcore IS PORT (
SysClk: IN STD_LOGIC; -- 100 MHz system clock from AJ15 FPGA pin
OutClk: OUT STD_LOGIC; -- 65MHz 180 deg phase shifted clock for video chip
hsync: OUT STD_LOGIC; -- Horizontal synchronization signal for D-sub connector
vsync: OUT STD_LOGIC; -- Vertical synchronization signal for D-sub connector
SYNC: OUT STD_LOGIC; -- !SYNC signal for the video chip
BLANK: OUT STD_LOGIC; -- !BLANK signal for the video chip
Red_out: OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- 8 bit red color signal
Green_out: OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- 8 bit green color signal
Blue_out: OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- 8 bit blue color signal
Red_in: IN STD_LOGIC_VECTOR (7 DOWNTO 0); -- 8 bit red color signal
Green_in: IN STD_LOGIC_VECTOR (7 DOWNTO 0); -- 8 bit green color signal
Blue_in: IN STD_LOGIC_VECTOR (7 DOWNTO 0); -- 8 bit blue color signal
Row_out: OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
Col_out: OUT STD_LOGIC_VECTOR(10 DOWNTO 0));
END COMPONENT;
begin
--USER logic implementation added here
video_ctrl_0 : VGAcore
port map (
SysClk => Bus2IP_Clk,
OutClk =>
hsync =>
vsync =>
SYNC =>
BLANK =>
Red_out =>
Green_out =>
Blue_out =>
Red_in => WFIFO2IP_Data(0 to 7),
Green_in => WFIFO2IP_Data(8 to 15),
Blue_in => WFIFO2IP_Data(16 to 23),
Row_out =>
Col_out => );
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= (others => '0');
IP2Bus_WrAck <= Bus2IP_WrCE(0);
IP2Bus_RdAck <= Bus2IP_RdCE(0);
IP2Bus_Busy <= '0';
IP2Bus_Error <= '0';
IP2Bus_Retry <= '0';
IP2Bus_ToutSup <= '0';
end IMP;
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Wed Apr 16 14:02:56 2008 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AWIDTH -- User logic address bus width
-- C_MAX_AR_DWIDTH -- User logic max data bus width of address ranges
-- C_NUM_ADDR_RNG -- User logic number of address ranges to be decoded
-- C_WRFIFO_DWIDTH -- Data width of Write FIFO
-- C_WRFIFO_DEPTH -- Depth of Write FIFO
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_Burst -- Bus to IP burst-mode qualifier
-- Bus2IP_RNW -- Bus to IP read/not write
-- Bus2IP_RdReq -- Bus to IP read request
-- Bus2IP_WrReq -- Bus to IP write request
-- IP2Bus_Retry -- IP to Bus retry response
-- IP2Bus_Error -- IP to Bus error response
-- IP2Bus_ToutSup -- IP to Bus timeout suppress
-- IP2Bus_AddrAck -- IP to Bus address acknowledgement
-- IP2Bus_Busy -- IP to Bus busy response
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2WFIFO_RdReq -- IP to WFIFO : IP read request
-- IP2WFIFO_RdMark -- IP to WFIFO : mark beginning of packet being read
-- IP2WFIFO_RdRelease -- IP to WFIFO : Return WFIFO to normal FIFO operation
-- IP2WFIFO_RdRestore -- IP to WFIFO : restore the WFIFO to the last packet mark
-- WFIFO2IP_Data -- WFIFO to IP : WFIFO read data
-- WFIFO2IP_RdAck -- WFIFO to IP : WFIFO read acknowledge
-- WFIFO2IP_AlmostEmpty -- WFIFO to IP : WFIFO almost empty
-- WFIFO2IP_Empty -- WFIFO to IP : WFIFO empty
-- WFIFO2IP_Occupancy -- WFIFO to IP : WFIFO occupancy
-- Bus2IP_ArData -- Bus to IP data bus for address ranges
-- Bus2IP_ArBE -- Bus to IP byte enables for address ranges
-- Bus2IP_ArCS -- Bus to IP chip select for address ranges
-- IP2Bus_ArData -- IP to Bus data bus for address ranges
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_AWIDTH : integer := 32;
C_MAX_AR_DWIDTH : integer := 64;
C_NUM_ADDR_RNG : integer := 1;
C_WRFIFO_DWIDTH : integer := 64;
C_WRFIFO_DEPTH : integer := 512
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
VideoClk: OUT std_logic;
horsync: OUT std_logic;
versync: OUT std_logic;
ChipSync: OUT std_logic;
ChipBlank: OUT std_logic;
Red_chip: OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- 8 bit red color signal
Green_chip: OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- 8 bit green color signal
Blue_chip: OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- 8 bit blue color signal
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_AWIDTH-1);
Bus2IP_Burst : in std_logic;
Bus2IP_RNW : in std_logic;
Bus2IP_RdReq : in std_logic;
Bus2IP_WrReq : in std_logic;
IP2Bus_Retry : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_ToutSup : out std_logic;
IP2Bus_AddrAck : out std_logic;
IP2Bus_Busy : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2WFIFO_RdReq : out std_logic;
IP2WFIFO_RdMark : out std_logic;
IP2WFIFO_RdRelease : out std_logic;
IP2WFIFO_RdRestore : out std_logic;
WFIFO2IP_Data : in std_logic_vector(0 to C_WRFIFO_DWIDTH-1);
WFIFO2IP_RdAck : in std_logic;
WFIFO2IP_AlmostEmpty : in std_logic;
WFIFO2IP_Empty : in std_logic;
WFIFO2IP_Occupancy : in std_logic_vector(0 to log2(C_WRFIFO_DEPTH));
Bus2IP_ArData : in std_logic_vector(0 to C_MAX_AR_DWIDTH-1);
Bus2IP_ArBE : in std_logic_vector(0 to C_MAX_AR_DWIDTH/8-1);
Bus2IP_ArCS : in std_logic_vector(0 to C_NUM_ADDR_RNG-1);
IP2Bus_ArData : out std_logic_vector(0 to C_MAX_AR_DWIDTH-1)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
signal RedIN: STD_LOGIC_VECTOR (7 DOWNTO 0);
signal GreenIN: STD_LOGIC_VECTOR (7 DOWNTO 0);
signal BlueIN: STD_LOGIC_VECTOR (7 DOWNTO 0);
-- these signals are from VGAcore entity
signal ColOUT: STD_LOGIC_VECTOR(10 DOWNTO 0) := "00000000000";
signal RowOUT: STD_LOGIC_VECTOR(10 DOWNTO 0) := "00000000000";
--these seignals are from writeFIFO
signal Column: STD_LOGIC_VECTOR(10 DOWNTO 0) := "00000000000";
signal Row: STD_LOGIC_VECTOR(10 DOWNTO 0) := "00000000000";
COMPONENT VGAcore IS PORT (
SysClk: IN STD_LOGIC; -- 100 MHz system clock from AJ15 FPGA pin
OutClk: OUT STD_LOGIC; -- 65MHz 180 deg phase shifted clock for video chip
hsync: OUT STD_LOGIC; -- Horizontal synchronization signal for D-sub connector
vsync: OUT STD_LOGIC; -- Vertical synchronization signal for D-sub connector
SYNC: OUT STD_LOGIC; -- !SYNC signal for the video chip
BLANK: OUT STD_LOGIC; -- !BLANK signal for the video chip
Red_out: OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- 8 bit red color signal
Green_out: OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- 8 bit green color signal
Blue_out: OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- 8 bit blue color signal
Red_in: IN STD_LOGIC_VECTOR (7 DOWNTO 0); -- 8 bit red color signal
Green_in: IN STD_LOGIC_VECTOR (7 DOWNTO 0); -- 8 bit green color signal
Blue_in: IN STD_LOGIC_VECTOR (7 DOWNTO 0); -- 8 bit blue color signal
Row_out: OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
Col_out: OUT STD_LOGIC_VECTOR(10 DOWNTO 0));
END COMPONENT;
------------------------------------------
-- Signals for user logic address range example
------------------------------------------
type BYTE_RAM_TYPE is array (0 to 255) of std_logic_vector(0 to 7);
type DO_TYPE is array (0 to C_NUM_ADDR_RNG-1) of std_logic_vector(0 to C_MAX_AR_DWIDTH-1);
signal ar_data_out : DO_TYPE;
signal ar_address : std_logic_vector(0 to 7);
signal ar_select : std_logic_vector(0 to 0);
signal ar_read_enable : std_logic;
signal ar_read_ack_dly1 : std_logic;
signal ar_read_ack : std_logic;
signal ar_write_ack : std_logic;
begin
--USER logic implementation added here
video_ctrl_0 : VGAcore
port map (
SysClk => Bus2IP_Clk,
OutClk => VideoClk,
hsync => horsync,
vsync => versync,
SYNC => ChipSync,
BLANK => ChipBlank,
Red_out => Red_chip,
Green_out => Green_chip,
Blue_out => Blue_chip,
Red_in => RedIN,
Green_in => GreenIN,
Blue_in => BlueIN,
Row_out => RowOUT,
Col_out => ColOUT);
-- Here goes the implementation of logic to draw graphic.
-- The state machine retreives RGB data and pixel position
-- data from writeFIFO, compares the pixel position with
-- current Row_out and Col_out of the VGAcore entity and
-- assignes this RGB data to the current pixel
Column <= WFIFO2IP_Data(24 to 34);
Row <= WFIFO2IP_Data(35 to 45);
DRAW_GRAPHIC: process (Bus2IP_Clk) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if (Column = ColOUT and Row = RowOUT) then
RedIN <= WFIFO2IP_Data(0 to 7);
GreenIN <= WFIFO2IP_Data(8 to 15);
BlueIN <= WFIFO2IP_Data(16 to 23);
else
RedIN <= "00000000";
GreenIN <= "00000000";
BlueIN <= "00000000";
end if;
end if;
end process;
------------------------------------------
-- Example code to access user logic address ranges
--
-- Note:
-- The example code presented here is to show you one way of using
-- the user logic address range features. Those *_Ar* IPIC signals
-- are dedicated to these user logic address ranges. Each user logic
-- address range has its own address space and is allocated one bit
-- on the Bus2IP_ArCS/Bus2IP_ArCE signals to indicated selection of
-- that range. Typically these user logic address ranges are used to
-- implement memory controller type cores, but it can also be used
-- in cores that need to access other address space (not C_BASEADDR
-- based), s.t. bridges. This code snippet infers 1 256x64-bit (byte
-- accessible) single-port Block RAM by XST.
------------------------------------------
ar_select <= Bus2IP_ArCS;
ar_read_enable <= ( Bus2IP_ArCS(0) ) and Bus2IP_RdReq;
ar_read_ack <= ar_read_ack_dly1;
ar_write_ack <= ( Bus2IP_ArCS(0) ) and Bus2IP_WrReq;
ar_address <= Bus2IP_Addr(C_AWIDTH-11 to C_AWIDTH-4);
-- This process generates the read acknowledge 1 clock after read enable
-- is presented to the BRAM block. The BRAM block has a 1 clock delay
-- from read enable to data out.
BRAM_RD_ACK_PROC : process( Bus2IP_Clk ) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( Bus2IP_Reset = '1' ) then
ar_read_ack_dly1 <= '0';
else
ar_read_ack_dly1 <= ar_read_enable;
end if;
end if;
end process BRAM_RD_ACK_PROC;
-- implement Block RAM(s)
BRAM_GEN : for i in 0 to C_NUM_ADDR_RNG-1 generate
constant NUM_BYTE_LANES : integer := (C_MAX_AR_DWIDTH+7)/8;
begin
BYTE_BRAM_GEN : for byte_index in 0 to NUM_BYTE_LANES-1 generate
signal ram : BYTE_RAM_TYPE;
signal write_enable : std_logic;
signal data_in : std_logic_vector(0 to 7);
signal data_out : std_logic_vector(0 to 7);
signal read_address : std_logic_vector(0 to 7);
begin
write_enable <= not(Bus2IP_RNW) and
Bus2IP_ArCS(i) and
Bus2IP_ArBE(byte_index);
data_in <= Bus2IP_ArData(byte_index*8 to byte_index*8+7);
ar_data_out(i)(byte_index*8 to byte_index*8+7) <= data_out;
BYTE_RAM_PROC : process( Bus2IP_Clk ) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( write_enable = '1' ) then
ram(CONV_INTEGER(ar_address)) <= data_in;
end if;
read_address <= ar_address;
end if;
end process BYTE_RAM_PROC;
data_out <= ram(CONV_INTEGER(read_address));
end generate BYTE_BRAM_GEN;
end generate BRAM_GEN;
-- implement Block RAM read mux
IP2BUS_ARDATA_PROC : process( ar_data_out, ar_select ) is
begin
case ar_select is
when "1" => IP2Bus_ArData <= ar_data_out(0);
when others => IP2Bus_ArData <= (others => '0');
end case;
end process IP2BUS_ARDATA_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_WrAck <= ar_write_ack;
IP2Bus_RdAck <= ar_read_ack;
IP2Bus_AddrAck <= ar_write_ack or ar_read_enable;
IP2Bus_Busy <= '0';
IP2Bus_Error <= '0';
IP2Bus_Retry <= '0';
IP2Bus_ToutSup <= '0';
end IMP;
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