Using concatenation operator in VHDL

lahrach · Mar 25, 2010

is this statement correct

clumn_fault : std_logic_vector(1 downto 0);

clumn_fault<= (outp_1 xor outp_2) & (outp_1 xor outp_3);

thanks

bigdogguru · Mar 25, 2010

Re: quik quetion vhdl

The concatenation operator in this case produces a data type equivalent to an element of the result data type STD_LOGIC_VECTOR. Hence the result will be the data type of STD_LOGIC_VECTOR, if outp_1, outp_2 and outp_3 are defined as STD_LOGIC.

So the following should work if the data types are defined correctly.

Code:

clumn_fault : std_logic_vector(1 downto 0); 

clumn_fault <= (outp_1 xor outp_2) & (outp_1 xor outp_3);

If you are still have problems, then another way to accomplish this would be:

Code:

clumn_fault : std_logic_vector(1 downto 0); 

clumn_fault(0) <= outp_1 XOR outp_2;

clumn_fault(1) <= outp_1 XOR outp_3;

This is assuming outp_1, outp_2 and outp_3 are STD_LOGIC.

bigdogguru · Mar 27, 2010

Re: quik quetion vhdl

Happened upon VHDLGuru's blog with a similar example:

Concatenation Operator in VHDL

Thought you might find it of interest.

Using concatenation operator in VHDL

lahrach

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Using concatenation operator in VHDL

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