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Using clock gating in latch based design : possible ?

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FAbouzeid

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Hi,

When using Flip-Flops in a design, Design compiler can detect them as registers and clock-gate them to reduce power.
But in case of using Latches in the same design, Design compiler do not detect them as registers and thus doesn't proceed with clock-gating of the latches.

Is it possible to do so ?
 

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