this is my main code. i have included functional model also. there it tells
" You must compile the wrapper file bram.v when simulating
the core, bram. When compiling the wrapper file, be sure to
reference the XilinxCoreLib Verilog simulation library"
what is a wrapper file and how to do this? pls help..
module ram (addr, clk, din, dout, we);
input [1 : 0] addr;
input [1:0] din;
input clk;
input we;
output [1 : 0] dout;
reg[1:0] memory[3:0];
reg[1:0] dout_r;
always @(posedge clk)
begin
if (we) memory[addr] <= din;
dout_r<= memory[addr];
end
// this is my instantiation part
bram ram (
.clka(clk),
.wea(we), // Bus [0 : 0]
.addra(addr), // Bus [3 : 0]
.dina(din), // Bus [15 : 0]
.douta(dout)); // Bus [15 : 0]
endmodule