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using bram in verilog

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student13

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Hello all,

I am trying to implement cordic in verilog, and need to use bram. can anyone help me with some example code like initialization, storing and reading.
 

bigdogguru

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Hi,

There's a few CORDIC cores available at:

OpenCores

Look under the Arithmetic Core Section, many of their cores are coded in Verilog

An excellent page on CORDIC, with examples and links:

Cordic Demo

Several examples of BRAM implementation are given in the "Synthesis and Simulation Guide" of ISE Software Manual.

BRAM related links:

Where to force Xilinx ISE to use block-rams

Xilinx BRAM Usage Instructions

Hope the info helps, if you need any additional assistance just let me know.
 

student13

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thanks for the info, but I am still not able to use bram. can you just provide me with full examples such as the verilog code and full project. I have tried but still not sble to do it. sorry for asking such trivial things.
 

permute

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both Xilinx and Altera have recommended coding styles for HDL designs. Both have examples of the coding constructs for BRAMs supported in the device and that can be inferred by HDL. Not all configurations are currently supported, and coregen/megafunction is still needed for some specific cases.

This should all be documented in the XST and Quartus manuals.
 

student13

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this is my main code. i have included functional model also. there it tells

" You must compile the wrapper file bram.v when simulating
the core, bram. When compiling the wrapper file, be sure to
reference the XilinxCoreLib Verilog simulation library"

what is a wrapper file and how to do this? pls help..

module ram (addr, clk, din, dout, we);
input [1 : 0] addr;
input [1:0] din;
input clk;
input we;
output [1 : 0] dout;
reg[1:0] memory[3:0];
reg[1:0] dout_r;
always @(posedge clk)
begin
if (we) memory[addr] <= din;
dout_r<= memory[addr];
end

// this is my instantiation part
bram ram (
.clka(clk),
.wea(we), // Bus [0 : 0]
.addra(addr), // Bus [3 : 0]
.dina(din), // Bus [15 : 0]
.douta(dout)); // Bus [15 : 0]

endmodule
 

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