jnors
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Hello everyone,
I am designing a PA for IEEE 802.11p using either one of these transistors:
-http://cdn.macom.com/datasheets/NDS-042r2%20NPT2018%20Preliminary%20datasheet.pdf
-http://www.cree.com/RF/Products/General-Purpose-Broadband-28-V/Packaged-Discrete-Transistors/CGH40010
I did load-pull for both of them and then instead of using source-pull i just used the conjugate of the input impedance seen by the transistor.
I was trying to design my matching networks, but even though they seem very close to what I want (in smith chart) when putting them in the design with the transistor the results detriorate a lot.
The optimization I'm using looks something like doccument1 attached.
I know that then I have to take into consideration the stability analysis and so on, but right now I would like to try and understand why this is happening.
The substrate using is one from Rogers which is able to go up until 10 GHz.
Thanks a lot,
I am designing a PA for IEEE 802.11p using either one of these transistors:
-http://cdn.macom.com/datasheets/NDS-042r2%20NPT2018%20Preliminary%20datasheet.pdf
-http://www.cree.com/RF/Products/General-Purpose-Broadband-28-V/Packaged-Discrete-Transistors/CGH40010
I did load-pull for both of them and then instead of using source-pull i just used the conjugate of the input impedance seen by the transistor.
I was trying to design my matching networks, but even though they seem very close to what I want (in smith chart) when putting them in the design with the transistor the results detriorate a lot.
The optimization I'm using looks something like doccument1 attached.
I know that then I have to take into consideration the stability analysis and so on, but right now I would like to try and understand why this is happening.
The substrate using is one from Rogers which is able to go up until 10 GHz.
Thanks a lot,