Using a SystemVerilog Generate in Quartus

[BartlebyScrivener]

I am using Quartus to try and synthesize a design and I keep getting the following errors when trying to use a generate block

Error (10170): Verilog HDL syntax error at LIB_PPE.sv(25) near text "genvar";  expecting an identifier ("genvar" is a reserved keyword )
Error (10644): Verilog HDL error at LIB_PPE.sv(30): this block requires a name

for code such as

  generate
    for (genvar i=0; i<N-1; i++) begin
      or  gate1  (l_intermediate[i], l_carry[i], i_priority[i]);
      and gate2  (o_grant[i], l_intermediate[i], i_request[i]);
      and gate3  (l_carry[i+1], l_intermediate[i], ~i_request[i]);
    end
  endgenerate

I found a setting to ensure that it knows my code is systemverilog, am I missing something else? The code works fine in modelsim.

 

[dave_59]

It is probably not supporting the SV syntax that lets you declare a variable as part of the for loop initialization, so pull the genvar i out of the for loop.

 

[BartlebyScrivener]

Thanks Dave, I think it fixed changing the code to ...

genvar i;
generate 
    for (i=0; i<N-1; i++) begin : PPE_SLICES
      or  gate1  (l_intermediate[i], l_carry[i], i_priority[i]);
      and gate2  (o_grant[i], l_intermediate[i], i_request[i]);
      and gate3  (l_carry[i+1], l_intermediate[i], ~i_request[i]);
    end
  endgenerate