I have a CDL file that I'd like to simulate, but I am not a digital designer and do not have access to the tools like Virtuoso or Synopsis.
What I do have is LTSpice. Is it possible to simulate the CDL in LTSpice?
The CDL has 400+ .SUBCKT statements which would be crazy to try to import 1-by-1 in LTSpice. What would be the best way to go forward?
Can you see the content of the file? Does it have the same format as the LTspice .asc file and is it not encripted? If so, try changing the extention using maybe notepad and see whether LTspice can read it.
Better still, you can show the content of the file here.
Can you see the content of the file? Does it have the same format as the LTspice .asc file and is it not encripted? If so, try changing the extention using maybe notepad and see whether LTspice can read it.
Better still, you can show the content of the file here.
I can open the file and see the sub-circuit definitions. I can also use LTSpice to automatically generate a symbol for the top-level sub-circuit listed in the CDL (the CDL file states what the top-level sub-circuit is). When I generate the symbol, there are 200 pins created based on what's listed in that circuits definition, but there are errors that occur like:
"Fatal Error: Port(pin) count mismatch between the definition of subcircuit "c45pl_top_signal_bitie_bcd3" and instance: "xu1:i876<0>"
The instance has more connection terminals than the definition."
It can be an actual mismatch in number of pins. Unfortunately, we don't know what pins your system should have.
There are a couple of things you could try though:
Open the spice model attribute for the model you just created and check whether there is anything written against SpiceModel. If there is, delete it and leave the space blank and check for the error again.