Hi,
Has anybody tried a 802.11a MAC in a FPGA?
Can somebody tell me the expected gate complexity for such a core, which Xilinx VirtexII chip may be suffecent??
Thanks for the answer Zhan
Does this estimate also include the gate count of Tx & Rx MAC unit?
Will there be any advantage developing the TX and Rx MAC in hardware? I have seen many cores where these parts are developed in software.
btw, i've been developing 802.11a digital PHY for intermediate frequency range (software defined radio). for example, demodulator with smoothed LS channel estimation/equalizing, full featured synchronization acquisition and tracking, and FEC, fits into virtex2 2000.
Usually a 802.11a MAC are software base as the spec is being changed (eg. fixing new security holes). If it is hardware base, it is bit hard to upgarde.
What functions do you want to implement in tx/rx MAC?
the partition of software and hardware is various according to different designs. if the software's process speed is fast enough, some functions, such as WEP, could be implemented in software. but the functions that need quick responds to the incoming data should be implemented in hardware. it is a tradeoff between performance and cost.