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using 100Kbits RAM in Spartan 3E XC3S250E

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bharathmanogna

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Hi All,

I want to use a 100Kbits Memrory (6400 words Deep 16 bit wide ) in Spartan 3E XC3S250E which acording to the datasheet has 216Kbits Total RAM(12 RAM blocks).the data sheets also says each RAM block contains 18Kbits of RAM divided into 16Kbits of data storage and 2K bits allocated to parity.

the only memory configuration which i found useful in each RAM Block was 1Kx16 (no parity).

So I have found that in order to implement 100Kbit RAM using the above configuration i need to use 7 RAM blocks,

As there is only one primitive(tools->language templates->Device premitive instantiation->spartan-3E->Block RAM->Single Port->RAMB16_S18) which is supported by the language template which is for 1Kx16.

how do i make these 7 blocks behave like a single RAM Block.are there any primitives for customising the RAM Blocks length and depth.

I have also tried using the Core generator but it only supports a 1K long RAM shift register.

Any help will be very much appreciated.

Thanks.

PS: i am using Xilinx ISE 14.4
 

TrickyDicky

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use the core generators, and it will generate the muxing logic for you.
 

bharathmanogna

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use the core generators, and it will generate the muxing logic for you.
Hi,
I have tried using core generator but it only has a 1Kbits RAM shift register!
Can you mention any specific document where i can get more details like a tutorial or a reference document
Thanks
 

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