It'said that the design using useful skew for timing optimization is susceptive of the operating condition variation-temperature,voltage,process...
And why?
zero skew clock tree also have clock buffers which have PVT variance.
Yeah..
Simple explaination...
To get the useful skew u may add some buf to clock path that buf changes its property depending on operating condition.. so the skew also will get affected because of PVT condition variation..
in use-full skew method upsizing and downsizing of buffers or inserting buffer will be done, obously gate delays will varies according to pvt conditions, so skew will get effected.
Too add one point to above responses to reduce this people use some specific clkbuffers in CLK TREE . These buffers are less senistive to PVT compared to others .
Still it will change but less change compared to datapath cells .
yes, usful skew is obey normal rule of CTS, which should be only used in special condition such as setup time can't be meet by all normal IPO such as buf and resize. So use the usful skew option in CTS carefully.