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usee of set_false_path in Actel/Synplify

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buenos

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set_false_path

Hi

I have a problem in using set_false_path constraint in actel/synplify flow.

I get these timing violations in my design:
(there is a loadable counter which runs from an asynchronous clock source. )

Code:
Starting Points with Worst Slack
********************************

                                      Starting                                                Arrival           
Instance                              Reference       Type         Pin     Net                Time        Slack 
                                      Clock                                                                     
----------------------------------------------------------------------------------------------------------------
Inst_businterfaces.ldt_csr_reg[3]     fpga_pciclk     DFN1C1       Q       ldt_csr_reg[3]     0.550       -7.077
Inst_businterfaces.ldt_csr_reg[2]     fpga_pciclk     DFN1C1       Q       ldt_csr_reg[2]     0.550       -7.072
Inst_businterfaces.ldt_csr_reg[1]     fpga_pciclk     DFN1E0C1     Q       ldt_csr_reg[1]     0.550       -6.797
Inst_businterfaces.lad_cl[3]          fpga_pciclk     DFN1C1       Q       lad_cl[3]          0.434       12.018
Inst_businterfaces.lad_cl_1[3]        fpga_pciclk     DFN1C1       Q       lad_cl_1[3]        0.434       12.018
Inst_businterfaces.lad_cl_2[3]        fpga_pciclk     DFN1C1       Q       lad_cl_2[3]        0.434       12.018
Inst_businterfaces.lad_cl_3[3]        fpga_pciclk     DFN1C1       Q       lad_cl_3[3]        0.434       12.018
Inst_businterfaces.lad_1[0]           fpga_pciclk     DFN1E0C1     Q       lad_1[0]           0.550       12.223
Inst_businterfaces.lad_1[1]           fpga_pciclk     DFN1E0C1     Q       lad_1[1]           0.550       12.223
Inst_businterfaces.lad_1[2]           fpga_pciclk     DFN1E0C1     Q       lad_1[2]           0.550       12.223
================================================================================================================


Ending Points with Worst Slack
******************************

                                   Starting                                       Required           
Instance                           Reference       Type         Pin     Net       Time         Slack 
                                   Clock                                                             
-----------------------------------------------------------------------------------------------------
Inst_businterfaces.ldt_reg[31]     fpga_pciclk     DFN0P1C1     D       I_121     7.984        -7.077
Inst_businterfaces.ldt_reg[30]     fpga_pciclk     DFN0P1C1     D       I_115     7.984        -6.453
Inst_businterfaces.ldt_reg[29]     fpga_pciclk     DFN0P1C1     D       I_109     7.984        -6.405
Inst_businterfaces.ldt_reg[27]     fpga_pciclk     DFN0P1C1     D       I_110     7.984        -6.091
Inst_businterfaces.ldt_reg[23]     fpga_pciclk     DFN0P1C1     D       I_127     7.984        -5.809
Inst_businterfaces.ldt_reg[28]     fpga_pciclk     DFN0P1C1     D       I_116     7.984        -5.781
Inst_businterfaces.ldt_reg[26]     fpga_pciclk     DFN0P1C1     D       I_129     7.984        -5.466
Inst_businterfaces.ldt_reg[25]     fpga_pciclk     DFN0P1C1     D       I_125     7.984        -5.418
Inst_businterfaces.ldt_reg[22]     fpga_pciclk     DFN0P1C1     D       I_126     7.984        -5.185
Inst_businterfaces.ldt_reg[21]     fpga_pciclk     DFN0P1C1     D       I_124     7.984        -5.137
=====================================================================================================

Worst Path Information
***********************


Path information for path number 1: 
    Requested Period:                        10.000
    - Setup time:                            2.016
    = Required time:                         7.984

    - Propagation time:                      15.062
    = Slack (non-critical) :                 -7.077

    Number of logic level(s):                12
    Starting point:                          Inst_businterfaces.ldt_csr_reg[3] / Q
    Ending point:                            Inst_businterfaces.ldt_reg[31] / D
    The start point is clocked by            fpga_pciclk [rising] on pin CLK
    The end   point is clocked by            System [falling] on pin CLK
...



I set these constraints in the SDC:


Code:
########   False Path Constraints  ########
set_false_path -from { fpga_pciclk } -to { ldt_reg }
set_false_path -from { ldt_reg } -to { fpga_pciclk }
set_false_path -from { ldt_ls_reg } -to { ldt_reg }
set_false_path -from { ldt_ml_reg } -to { ldt_reg }
set_false_path -from { ldt_mh_reg } -to { ldt_reg }
set_false_path -from { ldt_ms_reg } -to { ldt_reg }
set_false_path -from { ldt_csr_reg } -to { ldt_reg }

so, how can I disable this path for STA?
the counter =can be loaded from the PCI-based register when the timer is stopped in the LDT_CSR regisater, so it does not matter how much time it takes to propagate between the PCI regiaster and the counter.

another thing: "Requested Period: 10.000" where is this coming from??? PCI_CLK is 33MHz, so 30ns.

Added after 17 minutes:

it seems it does not care about my false path constraints.
 

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