use which tools to insert scan chain?

[xworld2008]

cadence atpg

now we use pks to insert scan chain, but someone tell me , cadence scan soft function isn't good.
i want to know they mean is insert scan chain tools or atpg tools. i think cadence and synopsys scan chain insert tools function will be same, but cadence atpg will be bad. is it?

 

[cheelgo]

insert scan dft synopsys

you can use Synopsys DFT-Compiler to do scan chain insertion.
for ATPG, means automatic pattern generation, generate test pattern for silicon production test.

 

[zyphor]

scan insertion mentor

synopsys's scan insertion tool: dft compiler, bsd compiler is easy to use, but synopsys's membist tool is rather bad, just better than do it manully. Mentor's membist tool: memory Architecture is really excellent and its scan chain generator :fast scan is also excellent , and better than synopsys's tetromax.

 

[joe2moon]

synopsys scan insertion

Scan Replacement/Insertion:
-- Synopsys: DFT Compiler
-- Cadence: BuildGate or RTL Compiler
----------------------------------------------------------------
Scan Stitching:
-- Synopsys: Design Compiler or Physical Compiler
-- Cadence: PKS or FE
----------------------------------------------------------------
ATPG: (automatic test pattern generation)
-- Synopsys: TetraMax
-- Cadence: Encounter Test
====================================

IMHO, " someone tell me , cadence scan function isn't good" means its scan insertion/stitching is not as flexible as Synopsys' one.

Since PKS or FE can only do scan-reordering while PC(w/ DFT Compiler) can do scan ordering.
-----------------------------------------------------------------

Encounter Test is also an excellent ATPG tool, see below.
https://www.cadence.com/products/digital_ic/encountertest/index.aspx

 

[leeenghan]

rtl compiler for scan insertion

If you company is using mainly Cadence tool, perhaps you should upgrade to RC for synthesis (and scan insertion), and Encounter-Test for boundary scan, scan-chain compression and ATPG.

For memory bist, the trend is toward using the solutions from the company providing the memory. One reason is because they are the only one that can add repairable feature to the BIST for the memory.

Regards,
Eng Han

 

[jarodz]

scan stitching in synopsys tool

Scan Replacement/Insertion:
IMHO, " someone tell me , cadence scan function isn't good" means its scan insertion/stitching is not as flexible as Synopsys' one.

Since PKS or FE can only do scan-reordering while PC(w/ DFT Compiler) can do scan ordering.

Can you explan more detail why cadence's scan insertion is not flexible and the
difference between scan-reordering and scan ordering?
Thx.

Sincerely,
Jarod

 

[cheelgo]

encounter scan insertion

in general, Mentor DFT ATPG tool is excellent and flexible & popular for current industry.

 

[hiben]

scan chain insertion rtl compiler

dft compiler is good for scan insertion. mentor fastscan is excellent for atpg generation. for mbist ,syntest is easy use and powerful

 

[anjali]

atpg cadence example

can anybody explain why cadence tool is not good.

 

[manu_leo]

encounter test

Hi,
use mentor's dftAdvisor to insert scan chains.

 

[kelvin_bao]

inserting boundary scan using cadence

can someone give some example script code of DFT Compiler?
.I want to learn DFT also,thank you !

 

[visualart]

FULL scan, I use the synopsys DFT compile
Part scan ,I run the mentor DFTAdvisor

 

[shankar]

magma automation tool can insert scan chain, if you need more details about this scan chain types and its operations contact me.

shankar