chetu
Junior Member level 2
verilog + .vh
hi
how to simulate the .vh files along with verilog files in model si
i have 2 files one is normal verilog ".v" file and other is ".vh" which contains simple tasks in verilog. i am calling that task in my .v file .
can anybody help me to simulate this?
or any other method?
hi
how to simulate the .vh files along with verilog files in model si
i have 2 files one is normal verilog ".v" file and other is ".vh" which contains simple tasks in verilog. i am calling that task in my .v file .
can anybody help me to simulate this?
or any other method?