Can anyone explain me that while building CTS, can we use buffer only or inverter and buffer both?
Bcz in my pnr tool (Olympus SOC), default setting of use of inverter is false in run_auto_cts command? so i have doubt that before running this command, can i enable use of inverter argument? OR can i go with buffer only?
what is preferable use of buffer only or both? And why? considering delay and power dissipation.
Can anyone explain me that while building CTS, can we use buffer only or inverter and buffer both?
Bcz in my pnr tool (Olympus SOC), default setting of use of inverter is false in run_auto_cts command? so i have doubt that before running this command, can i enable use of inverter argument? OR can i go with buffer only?
what is preferable use of buffer only or both? And why? considering delay and power dissipation.
You can use both, not an issue unless you end up in inverting the clock phase. Using inverters helps in reducing the area requirement, hence preferred in congested designs.
Use of inverter is preffered in congested design in that case if i dont have congestion and area requirement, but my main concern is about reducing delay and achieving better timing. so still i go with both (inverter and buffer) or i prefer to use only buffer?
Use of inverter is preffered in congested design in that case if i dont have congestion and area requirement, but my main concern is about reducing delay and achieving better timing. so still i go with both (inverter and buffer) or i prefer to use only buffer?
Buffer has higher delay inherently as it is nothing but back to back inverters by design. You can go with the buffer-inverter flow, but please make sure that the clock phases are as per requirement.
What I have observed is that a single buffer delay is not exactly two buffers delay.
So if u need less delay and less power dissipation then u go for more buffers.
If u need good slew and better pulse width invs will be the good choice.
Normally the tool adds buffers at the root and invs at the clock pins of the flops.
This I feel is the good approach.
What I have observed is that a single buffer delay is not exactly two buffers delay.
So if u need less delay and less power dissipation then u go for more buffers.
If u need good slew and better pulse width invs will be the good choice.
Normally the tool adds buffers at the root and invs at the clock pins of the flops.
This I feel is the good approach.
Hello pavanks,
you mean to say that single buffer delay is not exactly two inverter delay, am i right?
And can you tell me that how inverters help in improving, i mean achieving good skew and better pulse width? As buffer itself also contains two inverters only.
If you use buffers then skew will be high. You can also use inverters, but total number of inverters from clock definition point to clock pin of the FF should be even.
Make sure that the buffers or inverters which you are using in clock tree should have balanced rise and fall times. (i.e, RIse delay ~= Fall Delay ). Otherwise the pulse width of the clock signal will decreased and it will fail the functionality od design.