It sounds like the layer blocks SOI from being underneath the device. They must somehow prevent surface oxidation of the wafer so the device enclosed by this shape sits directly in the bulk (the wafer substrate). This would result in a non-soi device. You might use something like this if you want to control the back gate (body) of the device to adjust threshold voltage as vt in SOI is independent of body bias.
Hi,
If the techology in question is FD-SOI, the hybrid layer represents bulk opening areas on SOI subsrate, thus allowing you to build structures as conventional CMOS without SOI, or PTAP/NTAP connections to supply wells of SOI devices.