use of generate statement in verilog with loop

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sun_ray

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The generate statement is used along with for loop to instansiate an assign statements multiple times or to instansiate modules multiple times. But a for loop is capable of doing instansiation multiple times or to write assign statements multiple times with looping. So how does the generate statement is helping in doing multiple times? What is the use of generate statement then?

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sun_ray, do you ever do a search for any of your questions prior to asking? I guess you don't like to expend the effort and want others on the forum to search for you.

I normally just ignore all sun_ray posts (I think I need mrflibble's post eradication tool), but I thought looking this up and finding a good resource for this might stop others from screwing up generate/for loop usage (like that will ever happen...nobody knows how to "search" for anything).

Doing a search for "verilog generate statement" gave this as one of the results (the 2nd one for me).

One of the responses has a really nice explanation of where generate and for loops are allowed.
 
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