Hi,
A RESET is not necessarily a FAIL in ESD test. Some rules say the the device may temperarily go to an erroneous state but must to gain "controlled" state within a meaningful time. (often with the use of a watchdog)
Please check your ESD test rules.
Which ESD model do you use (MM, HBM, anything else...)
A schematic is only a part of the information needed.
We - or better say you - need to know where exactly the ESD current travles. An ESD probe has a GND connection and the HV tip. You need to be aware of the whole path between these two points. It´s stray inductance, voltage bounce on the path, traces nearby that become capacitively and/or magnetically coupled.
The ESD pulse is a high dV/dt pulse. What counts is rather trace impedance than trace resistance. This means you may use wide and thick traces with a resistance in the sub milliohms.. it does not matter. But the trace impedance may easily go to the hundreds of ohms. You need to think in HF not DC.
Rules: Keep the loop short. Keep the encolsed area small = signal the corresponding return_path need to be as cloase as possible. On a PCB this means: a GND_plane without cuts and other traces (in this area).
Klaus