use of Bram block in system generator as delay

[janaa]

Hello evreyone!

i m working with spartan3 fpga kit, for programming it i m using xilinx system generator tool box, now i want to use BRAM block of system generator to delay my data for 200 cycles kindly tell me how to use BRAM block for delay purposes.

 

[mrflibble]

By using a dual port BRAM as a circular buffer. You read from address N+1, and write to address N. Have the address counters go up to a number around 200 (I'm sure you can figure out the precise number and then wrap around to 0.

 

[TrickyDicky]

or just have the read counter lag the write counter by N. Reset both to 0 and only trigger the read counter when the write counter first gets to the N value. That way all you need is 2x counters, 1 compare and a latch.

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Or even better, reset the write counter to N.

 

[mrflibble]

I thought I'd leave the optimizations as an excercise for the reader. ;-) Personally I would also use the down counter version instead of the up counter version as in my example. But I find that up counters take on average 3000000 (*) whole microseconds less than down counters before the comprehension trigger triggers. So up counter it is for the example. ;-)

The exact number that is about 200 will also depend on the choice to use the bram output buffered or unbuffered. For this particular design I think I would go for adding the FFs on the output. Helps timings and easier routing outputs away from the BRAM output. Anyways, that's for the OP to decide if that is wanted or not.


(*) Average calculated for an ensemble sampling of silly and non-silly humans.


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For a bit of optimization fun you can do it with just one counter (== 2 CARRY4 + 8 FFs) and the same counter delayed by 1 cycle (another 8 FFs), and then do the compare of the upper 4 MSB with a single LUT4. Not that this 4-bit compare optimization matters terribly, since for 8-bit compare you'd use 2 LUT4s. And 1 or 2 LUT4's both end up in the same slices as those 8 FFs for the delayed counter anyways. The main savings is to use only 1 counter and a 1 cycle delayed version, which should use less slices than the 2 counter version.


Then again, maybe you do need the single LUT4 trick so you free up just enough routing resources. I forgot the particular detail needed for spartan-3 to do the routing in my head.

 

[janaa]

thanx 4 help



regards

janaa!

 

[janaa]

sorry
i could not implement the delay using the way you guys have told can you please show me any model where delay is implemented using BRAM cause i m confused about the input ports like wea,web ,ena and anb .

THANKS!

 

[mrflibble]

You can read the datasheet for the bram component to unconfuse yourself about those ports...