Non AMP

use GTECH (syn0psys) netlist in FPGA? (Xil inx ISE)

Thread starter stevepre
Start date Mar 2, 2006

Status: Not open for further replies.

Mar 2, 2006

#1

S

stevepre

Member level 4

Is it possible for ISE to read in GTECH netlist?

Thanks

Mar 8, 2006

#2

J

jcchan

Member level 1

Yes, it is possible to use GTECH netlist in FPGA

Mar 8, 2006

#3

S

stevepre

Member level 4

what library do I need to read before reading the GTECH netlist?

Thanks

Status: Not open for further replies.

Similar threads

AMD 7Series FPGA Configuration Debugging (INIT_B and DONE pins use)
- Started by dpaul
- Feb 23, 2024
- Replies: 1
PLD, SPLD, GAL, CPLD, FPGA Design
E
DSP slices in FPGA
- Started by engr_joni_ee
- Apr 3, 2024
- Replies: 1
PLD, SPLD, GAL, CPLD, FPGA Design
K
What's the difference between RAM and ROM with a coe files in Xilinx FPGA?
- Started by kevinwang65
- Mar 11, 2024
- Replies: 13
PLD, SPLD, GAL, CPLD, FPGA Design
R
problem of fpga
- Started by rllv24
- Mar 24, 2024
- Replies: 3
PLD, SPLD, GAL, CPLD, FPGA Design
A
PCIe power supply in FPGA
- Started by aminpix
- Oct 31, 2023
- Replies: 1
PLD, SPLD, GAL, CPLD, FPGA Design