My belief is that we cannot use the same clock clock rising and falling edges in synthesys, because there is no such flop which works with both rising and falling edges.
My belief is that we cannot use the same clock clock rising and falling edges in synthesys, because there is no such flop which works with both rising and falling edges.
Actually there is such flops, called "dual-edge triggered flip-flop". But I'm not sure that vendors have such stabdard cells and EDA tools can operate with it.