Aug 5, 2020 #1 P promach Advanced Member level 4 Joined Feb 22, 2016 Messages 1,199 Helped 2 Reputation 4 Reaction score 5 Trophy points 1,318 Activity points 11,636 I have some question about this usb implementation : https://github.com/avakar/usbcorev/ Could anyone explain why the two variables below actually transmit some "state machine status"-related data ?? Code Verilog - [expand]1 2 assign tx_j = j; assign tx_se0 = se0;
I have some question about this usb implementation : https://github.com/avakar/usbcorev/ Could anyone explain why the two variables below actually transmit some "state machine status"-related data ?? Code Verilog - [expand]1 2 assign tx_j = j; assign tx_se0 = se0;