promach
Advanced Member level 4
I have some question about this usb implementation : https://github.com/avakar/usbcorev/
Could anyone explain why the two variables below actually transmit some "state machine status"-related data ??
Could anyone explain why the two variables below actually transmit some "state machine status"-related data ??
Code Verilog - [expand] 1 2 assign tx_j = j; assign tx_se0 = se0;