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[SOLVED] usb3.0 Link Layer designing in FPGA

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zel

zel

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usb3.0 Link Layer

hi guys...
I am working on USB 3.0 Link Layer...
I have read the USB3.0 Spec but I still dont understand it..
can anybody tell me or give me the block diagram for it?
include the signals..please
 

Can i know in which you are currently implementing (i.e) in VLSI or any other platform.
Becoz i am also involving in the design of USB 3.0 in fpga and have the knowledge abot the usb2.0 .
 

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