air2008
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Actually, this one of the million half done projects that I have done. This one I want to come back to soon after I have my workshop set up again (I have moved 8 times in the past 3 years to/from 4 countries! :0 ) so this time I am not planning to move for a while and will be able to finish some of the projects.air2008 said:khach,
Farhad,
Thanks for your suggestions. There is a logic analyzer in my lab and I will try to capture the communication between the usb and cpld.
You said you have made a usb blaster for xilinx. How did you design the hdl codes in cpld?
air
air2008@gmail.com
First of all, RBF based on Altera's programming book (https://www.altera.com/literature/hb/cfg/cfg_cf52007.pdf) is just for Cyclone and other FPGA devices. For CPLDs, I don't think you can create an RBF file, but I maybe wrong.air2008 said:Hello,
I have known how to designing the CPLD based on PS mode. I write a programmer utility to download the *.rbf file to the FTDI usb chip and the CPLD send the RBF bitstream according to the PS mode.
Designing the code, if you know what you want to do is pretty straight forward. You either write it in a highlevel language like verilog or VHDL (in the case of Altera, you can write it in AHDL) or you make a schematic of the design using the internal logic blocks and then compile and create your POF or JED file.However, it could't be transparently compatible with @ltera's Quatus 2. How to design the CPLD in order to let the blastercompatible with Quatus without the need to write our own programmer utility?
air2008
air2008@gmail.com
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