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Usage of bit file of an FIR filter

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salma ali bakr

Advanced Member level 3
Jan 27, 2006
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i've the bit file of an FIR filter that i designed on system generator..i tried to use iMPACT in ISE to download this bit file on the FPGA but it starts to do the synthesis, the P&R, etc etc.. again....

how can this bit file be useful then??

also, how can i know where the inputs and outputs are if i have this bit file only without any ucf files generated...?



bit file usage

I would suggest running iMPACT as a stand-alone tool outside of ISE. (From Windows Desktop: Start, Programs, "Xilinx", Accessories, iMPACT. Replace "Xilinx" with whatever you named your install folder.) It cannot successfully run synthesis again because you do not have any source code, only the bit file.

With only the bit file, it is difficult to tell much about the design, as to inputs, output, logic, etc. This was intentional to protect the intellectual property of the original designer. Sure people will tell you that they can disassemble the bit file, but its way too much work for the result you get. Even if successful it will be just a bunch of LUTs and flops hooked together with meaningless net names.
Your best bet is to request the original design files from the developer.
Re: bit file usage

that input out put you can get from the simulink model designed.... you can give same input to the FPGA also.

if you are using any prebuilt model then there will be some doc for that and if you designed yourself then you should know that... anyways...system generator also generate the test benches. so you can search the input from that test benches..

Amit Gangwar
Re: bit file usage

thanks guys,

i made the design myself...

i know that i can generate an HDL netlist and then synthesize in ISE but i want to use the compilation option of bitstream...i want to know what i should do with the bit file has to have some stand-alone usage or else they wouldn't have included this option at all in the tool...even if i was able to download it on the FPGA, how will i test it real-time...i know that i can do hardware co-simulation...but that's just a simulation...what if i need it to actually work and give it inputs and receive outputs from it...?!

the design inputs and outputs are only known to me if i generate an HDL, cause with the help of the UCF i can know which port is where exactly on the board...but with this bit file, there's nothing that indicates what is where....cause it's the ONLY file generated..

i was just reading an article in Xcell journal about system generator, and it mentions that one doesn't have to know an HDL in order to use it, cause it makes automatic code generation...!!! ok, how can i -"without" any hardware background- make this bit file function on the FPGA and how can i test it real-time...?!


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