In VHDL, you could use GENERIC and use for loop to instantiate variable number of modules, if need be. The synthesizer would then unfold the for loop and basically replicate the code as required.
My question is : Do we have the same approach for verilog? For instance, I have a submodule My_MODULE and I need to instantiate it X times where X is defined as PARAMETER (fixed). Then how would the naming for those generated modules would be?
I think in verilog to do this it's much simpler. For Verilog, you might want to try something like this:
Code:
module higher_module // define a module to instantiate the My_MODULE
parameter x = 10; // declare a paramter x, set it to 10
input [x:0] a; // create input ports for My_MODULE
output [x:0] b; // create output ports for My_MODULE
My_MODULE xmod[x:10] (b, a); // create an array of 11 My_MODULES and connect ports
endmodule
Then to specify a single My_MODULE in the array you would do:
Code:
xmod[x-1]
for the MSB and
Code:
xmod[0]
for the LSB
Also, you can do slices or parts like this: