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[SOLVED] URGENT! Help on 8-bit UP counter again!

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karthiga05

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Hi guys! I've done my codes for my 8-bit UP counter already.. I really need someone to help me with the values for the 1st and 2nd clockcycle for c_out(0) to c_out(7) and carry(0) to carry(6).its highlighted in red. line by line. Would really appreciate ure help! thanks in advance!

Here is my code::


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity my_counter is
port(count: Out std_logic_vector(7 downto 0);
clk: in std_logic;
reset: in std_logic);
end my_counter;

architecture behav_my_counter of my_counter is

signal c : std_logic_vector(7 downto 0) := "00000000";

begin

ctr:

process(clk,reset)
variable carry : std_logic_vector(7 downto 0) := "00000000";
begin

if reset'event and(reset = '1') then
c <= (others => '0');

elsif clk'event and (clk = '1') then
--i am adding "00000001" to 'c'.
--this is done using basic logic gates.
-- the equation for full adder is simplified and written below.
--full adder equations are:
-- sum = A xor B xor Carry.
-- carry = (A and B) or (A and carry) or (B and carry).
--subsititue B with "00000001" here and you will get the below equations.
c(0) <= not c(0);
carry(0) := c(0);

c(1) <= c(1) xor carry(0);
carry(1) := c(1) and carry(0);

c(2)<= c(2) xor carry(1);
carry(2) := c(2) and carry(1);

c(3)<= c(3) xor carry(2);
carry(3) := c(3) and carry(2);

c(4)<= c(4) xor carry(3);
carry(4) := c(4) and carry(3);

c(5)<= c(5) xor carry(4);
carry(5) := c(5) and carry(4);

c(6)<= c(6) xor carry(5);
carry(6) := c(6) and carry(5);

c(7)<= c(7) xor carry(6);



end if;

end process;
count <= c;


end behav_my_counter;

---------- Post added at 16:22 ---------- Previous post was at 16:19 ----------

c(0) <= not c(0);
carry(0) := c(0);

c(1) <= c(1) xor carry(0);
carry(1) := c(1) and carry(0);

c(2)<= c(2) xor carry(1);
carry(2) := c(2) and carry(1);

c(3)<= c(3) xor carry(2);
carry(3) := c(3) and carry(2);

c(4)<= c(4) xor carry(3);
carry(4) := c(4) and carry(3);

c(5)<= c(5) xor carry(4);
carry(5) := c(5) and carry(4);

c(6)<= c(6) xor carry(5);
carry(6) := c(6) and carry(5);

c(7)<= c(7) xor carry(6);


I would like to knw the values of each c() and carry().
 

FvM

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What you need is:
- to know the meaning of logic operations and, xor, not
- to know how synchronous logic works, particularly the different behaviour of variable := and signal <= assignments
- pencil and paper

Why don't you try yourself and present the results?
 

karthiga05

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I tried but i couldnt get the answer. thts why i asked for help here. and i do knw the meaning of and,xor and not.
 

alexan_e

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Are you aware of the difference between signal and variable assignment?

c(0) <= not c(0); // the new value of c(0) will be valid after the process ends
carry(0) := c(0); // here you assign the old value of c(0) to a variable with immediate effect.

VHDL Tutorial - Signals and Processes

Alex
 

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