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From my perspective, when a pipeline is interlocked, it will generate a pipeline stall. Who can tell me the detail differences between interlock and stall. Thanks.
From the book written by John L. Hennessy and David A. Patterson, Computer Architecture-A Quantitative Approach, 4th edition, in appendix A, A-20.The following is the content:
The load instruction has a delay or latency that cannot be eliminated by for-warding alone. Instead, we need to add hardware, called a pipeline interlock, to preserve the correct execution pattern. In general, a pipeline interlock detects a hazard and stalls the pipeline until the hazard is cleared. In this case, the interlock stalls the pipeline, beginning with the instruction that wants to use the data until the source instruction produces it. This pipeline interlock introduces a stall or bubble, just as it did for the structural hazard. The CPI for the stalled instruction increases by the length of the stall (1 clock cycle in this case).
From my perspective, if a pipeline is interlocked, it must generate a stall.
what is your opinion? Thanks.
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