It seems to me that it's just a typical synchronous logic and glitch doesn't matter. The glitch happens all the time within the comb logic until all the signal settles, but what matters is the signal state upon the capturing edge of the clock. Since both of Input and COUNT is synchronous, I don't see the reason why you want to treat bit_stuff_* as async.
Furthermore, if you treat both of bit_stuff_* as 'async' like you said, on the receiving block, you probably need make sure that there is ZERO delay difference (which is impossible) between bit_stuff_error and bit_stuff_detect otherwise when these two signals go out of sync each other due to a small time lag, your receiving block may go into a state not expected like both of them is '1'.
if you want to avoid glitch, you have only 2 options. One is flopping it, another is picking the input patterns that don't cause a glitch. For example, if 2 input AND, avoid 10 -> 01 transition.