ranbi
Newbie level 5
i need to convert En to bit_vector to do the srl in vhdl and I need to reconvert back to std_vector_logic for the second operation plz can anyone help me out with the correct syntax:
my part code:
signal En: std_logic_vector (31 downto 0);
En<= En srl 8;
Thanks
my part code:
signal En: std_logic_vector (31 downto 0);
En<= En srl 8;
Thanks