[SOLVED] Upper limit of carrier frequency for PWM

[mrinalmani]

Although carrier frequencies in the range of 20kHz to 30kHz are commonly heard of, what may be a practical upper limit to carrier frequency? Is it anywhere close to say, 100kHz or perhaps even higher?

 

[FvM]

You are talking about what? High or low voltage, hard or soft (resonant) switching, MOSFET or IGBT power stages?

 

[dick_freebird]

I have personally designed (and production released) POL
DC-DC converter ICs with integrated FETs that exceed
85% efficient at 5MHz, 5A.

The higher you want to go in voltage, the fewer choices
you have and the more difficult it is to keep efficiency at
high frequencies.

Some things you would prefer to do for efficiency in some
topologies will limit your switching frequency to much lower.
Soft switching means slower switching; good on resistance
often comes at the cost of driven input capacitance against
a finite gate driver strength, causing leisurely rise/fall times
which must be kept to a small fraction of total cycle and
so on.

But short answer, we're well past that range in the niches
where it's practical.

 

[mrinalmani]

Thanks for the reply!
Anyway, to make it more precise... I was talking of a MOSFET inverter and hopefully a resonant based, for faster speeds.

The current indeed is around 5A but the power levels are higher. 2KVA at 415V.
That DC-DC converter sounds unbelievably impressive, however I do not suppose that such switching speeds will be possible for a 2KVA, 400V inverter operating at a minimum efficiency of 95%

For such applications, what speed would be a considered high and close to state of the art?

 

[dick_freebird]

Power MOSFET based bricks today run at 100-200kHz
commonly. But switching losses are already significant
there. An EPC GaN FET would beat them soundly but
you can't get them in 600V ratings yet. GaN FETs can
be run in the MHz range without much switching loss,
although they have their own safe operation issues
about the gate overdrive level.

EPC has demonstrated efficieicies consistent with your
goal but I question whether you will get 95% minimum
across the operating envelope (min load to max load,
min VIN to max VIN). Either there's a pound of magic
in that half-pound box, or something else is likely left
on the table (like a lot of excess copper and iron).

The GaN FETs suffer from a lack of good drivers. There
are drivers, just not good ones. You probably can't
push the GaN FETs past 10MHz with today's parts.
I worked on a much higher speed, high voltage capable
driver at my last job but left before seeing the silicon.
You ought to keep an eye on what EPC is doing, they
keep busy and keep trying out other peoples' drivers
so maybe there's something new there for you.

 

[mrinalmani]

Thanks for the detailed reply.
I am reluctant to participate in a competition which is all about designing an inverter with the highest power density. The winner will be the one having the smallest volume of inverter for a 2KW output. The input is 415VDC and output 240VAC.
Price is not a factor. Free use of wide-band devices such as GaN can be made.

I am not at all familiar with GaN or SiC devices. Should they be considered? Should I expect the competitors to be working in MHz range? (Keeping in mind the power output). There is also a minimum efficiency requirement of 95% at full load.

What in your opinion would be a clean winer. Si or GaN? Or is it a tough competition?

 

[FvM]

Which design parameters are imposing an ultra-high PWM frequency?

The inverter won't need a transformer. So the output filter inductor and capacitors, if any, are the main frequency related components, possibly the bus capacitor.

If filter components are counting for the form factor, above a certain frequency, efficiency advantages and respective smaller heat sinks can be traded against filter comonent size.

 

[mtwieg]

He/she is referring to the **broken link removed**...

I'd estimate that the winners will have at least 98% efficiency, probably switching in the hundreds of kHz range. Not much point in going higher if you're only synthesizing 60Hz.

IMO the bigger obstacle with the design is getting the low frequency input current ripple to <20%. You need some serious capacitors for that, and no fancy switching devices will help with that.

 

[schmitt trigger]

He/she is referring to the **broken link removed**...

I'd estimate that the winners will have at least 98% efficiency, probably switching in the hundreds of kHz range.
t.

How reliable are the SiC semiconductors?
When I worked with a power supply company over 10 years ago, we gave some serious consideration to these, but the reliability gurus found out that for the market we were serving, (high uptime servers), they simply weren't reliable enough, or we didn't fully understand them.
We even built over 100 units for evaluation, and when a failure occurred, it was on the SiC boost diode of the PFC stage.
But that was over a decade ago.

 

[Mr.Cool]

you're reliability guru's scare easily. SiC is very reliable because it has such low losses and junction temperature easily over 200C. i said EASILY.
i built a 50kW inverter with SiC at 600V and hit 98% efficiency over entire range. that was like 7 years ago or so. i also met MIL-STD 704 & 160 for noise.

this competition has no price or reliability target which makes me sad. why build a gate driver with desaturation detection when it just takes up room? why use sine-PWM (for example) when you can use some way more exotic - and yet unproven - switching algorithm. put everything on an ASIC to reduce volume. use pin-fin or some other fancy heat sink that costs A LOT of money. all these things will win you the competition, but will fail you in real world. its too bad Google cares only for pie in the sky solutions..

oh. and they get to use the world as their think tank for bare bottom price of 1 million for their Little Box Challenge.

 

[schmitt trigger]

you're reliability guru's scare easily. SiC is very reliable because it has such low losses and junction temperature easily over 200C. i said EASILY.
i built a 50kW inverter with SiC at 600V and hit 98% efficiency over entire range. that was like 7 years ago or so. i also met MIL-STD 704 & 160 for noise.

This is why I mentioned "over a decade ago". It could have been as much as 15 years...
The improvement and evolution of SiC devices between that time frame and yours (7 years) is light years away.

 

[dick_freebird]

SiC (and other wide bandgap devices) are a moving target, true.
They also by their nature encourage people to design with high
power density potential when things go wrong. In my work I am
exposed to a lot of abnormal conditions and the SiC diodes,
FETs, SJTs have such high applied fields that if they do enter
breakdown (even localized) it's all over unless there is external
current limiting - and there isn't, in an efficient power supply.
One relativistic heavy ion will ruin your whole day. And the same
might well be true for a latent material defect, of which all of
these compound semiconductors are chock-full (by silicon
standards). I don't believe industry has come around to the
same sort of derating tribal knowledge that silicon power devices
"enjoy". And certainly not at the extremes of application
environment and abnormal conditions. What the marketing guys
dangle in front of you, is not what you can actually get away
with in the hard corners.

 

[schmitt trigger]

I don't believe industry has come around to the
same sort of derating tribal knowledge that silicon power devices
"enjoy". And certainly not at the extremes of application
environment and abnormal conditions. What the marketing guys
dangle in front of you, is not what you can actually get away
with in the hard corners.

Thanks Dick, your comment has refreshed my memory. A similar argument was made made back then.

As part of the contract, there was a significant testing period on which large batches of SiC devices were evaluated. Temperature, withstanding voltage, avalanche, you name it, it was tested.
Simultaneously, another large batch consisting of mature Silicon devices was subjected to identical tests.
There were plenty of funds available, as this would be eventually be used for a US government project, details of which weren't disclosed to us, other than it had to have very low FITs (failures In Time).

At the end of a loooong evaluation, more SiC devices had failed than the traditional Silicon ones. And the important thing was the SiC device manufacturers could not give a plausible explanation for the failure mechanism and thus a corrective action. That was what -I believe- gave us cold feet.
But again, materials science has advanced a lot in a decade and a half. They may have a much better grip on SiC reliability nowadays.