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upcounter and updown counter power and area

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tv123

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Will there is be power and area difference for an 6 bit upcounter and 6 bit updown counter?
 

TrickyDicky

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Probably. Why not build them and find out.
 
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mrflibble

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I'd expect that a 6-bit updown counter will take at least as much power/area as 6-bit upcounter, and possibly a bit more. I'd expect area increase to be slightly more pronounced than power increase. But as TrickyDicky said, try and find out for yourself. :)
 

tv123

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Is there a possibility of replacing a up/down based frequency divider by a upcounter one with a rst signal

i.e, if a max count is given and an updown counter counts two and fro to max and to zero with a high frequency signal.

Instead of this can i use an up counter which counts to max and then rst and again count to max and so on.

If rqrd i can give more explanation
 

TrickyDicky

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If you are in an FPGA - you should not be using any sort of counters for frequncy division, unless you are generating a clock enable. Creating new clocks should be done as the output of an MMCM or PLL
 

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