Unwanted pulse width in complementary pwm using msp430g2553

[Tahsinhossain]

Hi,

I am trying to generate 2 complementary sinusoidal PWM signals using msp430g2553. I want to use those as unipolar SPWM to drive a full-bridge.

Spec:
Reference Signal = 50 Hz
Triangular Signal = 2.5 kHz
pwm period = 0.4ms or 400 us
dead time between 2 signals = 1 us (this is why I am using up/down mode and Timer1_A3)

However, I am getting below output in the oscilloscope:


I am not sure why few pulses are out of shape. What am I doing wrong? Below is my code for your review. Any help is highly appreciated.

#include  <msp430g2553.h>

const unsigned int phalfcycle[25] = {100, 110, 120, 129, 139, 147, 155, 162, 168, 172, 176, 179, 180, 180, 179, 176, 172, 168, 162, 155, 147, 139, 129, 120, 110};
const unsigned int complementary[25] = {99, 109, 119, 128, 138, 146, 154, 161, 167, 171, 175, 178, 179, 179, 178, 175, 171, 167, 161, 154, 146, 138, 128, 119, 109};

unsigned int index = 0;

void main(void)
{
  WDTCTL = WDTPW + WDTHOLD;                 // Stop WDT

  //Calibrate DCO for 1MHz operation
  BCSCTL1 = CALBC1_1MHZ;
  DCOCTL = CALDCO_1MHZ;

  P2DIR |= BIT1 + BIT4;                            // P2.1 and P2.4 pwm output

  TA1CCR0 = 200 - 1;                               // PWM Period/2; period is 0.4ms or 400us

  TA1CCTL0 = CCIE;									// CCR0 interrupt
  TA1CCTL1 = OUTMOD_6;                         // CCR1 toggle/set
  TA1CCTL2 = OUTMOD_2;							// CCR2 toggle/reset as complementary
  TA1CTL = TASSEL_2 + MC_3 + TACLR;                  // SMCLK, up-down mode

  _BIS_SR(LPM0_bits + GIE);                       // Enter LPM0
}


#pragma vector=TIMER1_A0_VECTOR						// ISR for CCR0
__interrupt void Timer_A0 (void)
{
	TA1CCR1 = phalfcycle[index] - 1;
	TA1CCR2 = complementary[index] - 1; 			// deadtime = 1us

			index = index + 1;
			if(index == 25)
			{
				index = 0;
				P2SEL ^= BIT1;
				P2SEL ^= BIT4;
			}

}