module Counter(q, clk);
output reg [15:0]q;
input clk;
always@(posedge clk) begin
q <= q+1;
end
endmodule
what happens at 2^16 clock edges? apparently its not turning to 0.
this is the most confusing for me. If you didn't write it on your own....what did you write then?I don't know how this became the title...
this is the most confusing for me. If you didn't write it on your own....what did you write then?
Makes no difference for synthesized hardware.In my program, I wrote q <= q+1;
Is it necessary to write 16'b1 instead of 1, or is it fine like this.
q <= 1 writes unsigned decimal 1 to the register vector, setting all register bits.Similarily, if I have a register like this:
output reg[15:0] q;
What would happen if I write:
q <= 1;
Is there a chance it initializes only the last bit? Or will it initialize the lsb to 1 and all others to 0?
Sure, q[0] <= 1.Is there a chance it initializes only the last bit?
So, MSB means MSB of "q" --> q15Now for the other questions:
MSP was a typo for MSB (maybe due to the fact that I'm a heavy MSP430 user).
MSB, data2 etc... can be found on the picture I posted, these are the name of the traces on the oscilloscope I am using.
second bit is the same as data2.
Why now "r" ? In the code I see just "q"...I have setup the r[15:0] output
The binary counter described in post #1 has already DFFs at the outputs. The adder output is only internal and not visible unless routed to pins explicitly.A 16 bit adder needs to calculate the carry from bit to bit (depending how it is implemented).
This needs time. In worst case there are 15 gates connected in series.
Are you sure the the FPGA can run a 16 bit adder with 50MHz clock?
(Usually it shouldn't be a problem.)
Here I need to repeat my question about timing constraints and error/warning messages...
To avoid glitches (caused by combinatorial logic) one it's generally a good idea to add a DFF to the outputs.
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