vrunda
Newbie level 4
hi.,
i had done the schematic of a circuit in Dsch3 and generated the verilog code for the same using the option in "make a verilog file". This verilog code is then simulated in Xilinx 12.4. the code has no syntax error and was simulated successfully. but when i need to see the synthesis report it is showing some error like "inv.v" line 25: Unsupported Switch or User Defined Primitive". so can anyone help me to come out of this problem.. kindly pls help me.
thank u,
i had done the schematic of a circuit in Dsch3 and generated the verilog code for the same using the option in "make a verilog file". This verilog code is then simulated in Xilinx 12.4. the code has no syntax error and was simulated successfully. but when i need to see the synthesis report it is showing some error like "inv.v" line 25: Unsupported Switch or User Defined Primitive". so can anyone help me to come out of this problem.. kindly pls help me.
thank u,