Unsupported Event Control Statement - Verilog HDL

Valerius · Nov 4, 2015

Hi,

I'm trying to debug my code which takes 4x4 keypad inputs and displays the corresponding key index to the seven segment 2 digit display. However I encountered with the following warning:

Code:

ERROR:Xst:850 - "topModule.v" line 60: Unsupported Event Control Statement. 
ERROR:Xst:850 - "topModule.v" line 63: Unsupported Event Control Statement.

which points to the indicated areas in my code:

Code:

module topModule(pROW, pCOL, CLK, AN, sevenSegment);
	
	input CLK;
	output [3:0] pROW; //Row to be written
	input [3:0] pCOL; //Column to be read
	output reg [3:0] AN; //Anode output
	output reg [6:0] sevenSegment; //Seven Segment data to display
	
	reg [3:0] currentValue; //Register that holds the last output value BUT it is 1 less !!!
	
	wire [6:0] DigOUT1; //Both digit values
	wire [6:0] DigOUT0;
	wire [3:0] keyOUT; 
	wire EN1, EN0;
	
	parameter One = 7'b1001111; //When the index value is bigger than nine, display
										 //the tenths decimal digit one with this parameter
	
	keypadScanner keySch(pROW, pCOL, keyOUT, CLK);
	sevenSegDecoder ssegDECDig1(One, DigOUT1,	EN1); 
	sevenSegDecoder ssegDECDig0((keyOUT + 1), DigOOUT0, EN0); //Add 1 since we lost 1 in keySch
	
	assign EN1 = 1'b1 ? keyOUT > 9 : 1'b0;
	assign EN0 = 1'b1;
	
	//2:1 Multiplexer which displays the digits about 800Hz
	reg [15:0] count;
	
	wire ticker;
	
	always @(posedge CLK) count <= count + 1;
	
	assign ticker = &count;
	
	always begin
		currentValue <= keyOUT;
		if(currentValue > 9)	begin
			AN <= 4'b1110;
			sevenSegment <= DigOUT0;
			@(posedge ticker)     //<------ POINTS TO HERE
			AN <= 4'b1101;
			sevenSegment <= DigOUT1;
			@(posedge ticker);    //<----- POINTS TO HERE
		end
		else begin
			AN <= 4'b1110;
			sevenSegment <= DigOUT0;
		end
	end
endmodule

The reason that I have this event control is to create my own specific timing control on my FPGA board. Since it is not a simulation I had to do it via counter.

Thank you.

Valerius · Nov 4, 2015

ads-ee said:
@(posedge ticker) is not synthesizable, it's only used in simulation testbenches as an event control to wait until the rising edge of the signal ticker.

For edge triggered logic that is synthesizable you have to use always @ (posedge ticker) if you want to synthesize the module. As ticker is used as a clock this is a bad design especially as it uses the output of a multi input AND gate. You should probably place all your logic in the always @ (posedge CLK) block and directly use the value of count to do the stuff with AN that you want (instead of trying to write a software procedural implementation).

Here is an example..

Code Verilog - [expand]
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always @ (posedge clk) begin cnt <= cnt + 1; if (cnt == 3) begin x <= 1'b1; // pulse while cnt is 4 end else if (cnt == 8) begin x <= 1'b1; // pulse while cnt is 9 end else if (cnt == 16) begin x <= 1'b1; // pulse while cnt is 17 end else begin x <= 1'b0; end end

You need to get a book on Verilog, the code you are writing is not synthesizable code nor does it follow synthesizable templates. Verilog is used to describe hardware and is not written like a programming language. Unless you know what your circuit looks like how are you going to describe it? (i.e. the code ends up looking like a piece of rubberware - 1/2soft-1/2hard-ware).

Yes, probably because I just started learning Verilog I was trying to slow down my clock to use it on my 2 digit seven segment display, My clock has a frequency of 50 Mhz and I need to slow it down to 800Hz, do you have any suggestions on doing this?

Valerius · Nov 4, 2015

Thanks for your kind words Yes its been couple of weeks since I started learning Verilog. And I'm aware that its just a typo.. correct version would be: assign EN1 = keyOUT > 9 ? 1'b1 : 1'b0;

ads-ee · Nov 4, 2015

@(posedge ticker) is not synthesizable, it's only used in simulation testbenches as an event control to wait until the rising edge of a signal.

For edge triggered logic that is synthesizable you have to use always @ (posedge ticker) if you want to synthesize the module. This is a bad design as ticker is used as a clock when it is produced by the output of a multi input AND gate. Conbinational logic used to generate clocks will almost certainly result in glitches. You should place all your logic in the always @ (posedge CLK) block and directly use the value of count to do the stuff with AN that you want (instead of trying to write a software procedural implementation).

Here is an example..

Code Verilog - [expand]
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always @ (posedge clk) begin
  cnt <= cnt + 1;
 
  if (cnt == 3) begin
    x <= 1'b1; // pulse while cnt is 4
  end else if (cnt == 8) begin
    x <= 1'b1; // pulse while cnt is 9
  end else if (cnt == 16) begin
    x <= 1'b1; // pulse while cnt is 17
  end else begin
    x <= 1'b0;
  end
end

You need to get a book on Verilog, the code you are writing is not synthesizable code nor does it follow synthesizable templates. Verilog is used to describe hardware and is not written like a programming language. Unless you know what your circuit looks like how are you going to describe it? (i.e. the code ends up looking like a piece of rubberware - 1/2soft-1/2hard-ware).

- - - Updated - - -

what the heck is this?

Code:

assign EN1 = 1'b1 ? keyOUT > 9 : 1'b0;

it will always select keyOUT >9 and if it's true it will be 1 otherwise it's 0. I don't think you know how to write Verilog code, it's not VHDL...

Code:

// The correct way to use "?"
assign <wire_name> = <comparision> ? <true output> : <false output>;

- - - Updated - - -

Based on this sample of code I'd wager your submodules probably have issues to.

- - - Updated - - -

Valerius said:
Yes, probably because I just started learning Verilog I was trying to slow down my clock to use it on my 2 digit seven segment display, My clock has a frequency of 50 Mhz and I need to slow it down to 800Hz, do you have any suggestions on doing this?

800 Hz is way to fast to see changes on an display...

Code Verilog - [expand]
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reg [25:0] cnt = 0;
reg onesec = 0;
 
always @(posedge clk) begin
 
  if (cnt < 50000000-1) begin  // counts from 0 to 49999999 back to 0
    cnt <= cnt + 1;
  end else begin
    cnt <= 0;
  end
 
  onesec <= (cnt == 50000000-1);
 
  if (onesec) begin
    // logic to do something every 1 second.
  end
end

Unsupported Event Control Statement - Verilog HDL

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