The output signals are generated by decoding current_state in combinational logic, glitches can possibly occur due to different logic delays. Picoseond glitches should not be expected to appear actually at a hardware pin. But to assure glitch free operation of decoded ouputs from FSM without depending on special logic family features, the signals should be registered to my opinion.
A registered signal would be implied, when assigning the output in a clock synchronous process, e. g. together with assignment of current_state. But this results in a delay of one clock cycle. Otherwise, you would need a decoder in clock synchronous process driven by next_state. But I don't know your design requirements, you should be able to find a solution considering the behaviour of combinational and clock synchronous logic.
The outputs of the FSM, are actually async reset signals to other modules.. Since they are async, i cannot afford the glitch. Also i cannot afford the delay of an extra clock cycle.
I guess, if i change the resets to synchronous resets, it might solve the problem.
Yes, I think so. Additionally, an asynchronous reset always implies a risk of getting undefined states in the resetted entity, if release of reset coincides with next clock edge.