sandy2811
Junior Member level 3
Hi,
In my simple design, I am giving some inputs and it is difficult for me to know which signal act as a clock. i.e. only "y" act as a clock or both "x" and "y" act as clock.
In my simple design, I am giving some inputs and it is difficult for me to know which signal act as a clock. i.e. only "y" act as a clock or both "x" and "y" act as clock.
Code:
module my_design (q, d, x, y);
input x, y, d;
output reg q;
always@(posedge x or posedge y)
begin
if(x)
q <= 1'b0;
else
q <= d;
end
endmodule
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