tj.diego
Junior Member level 2
Hi floks,
i'm back again with a new error!!!
i wrote the vhdl code of a kogge-stone radix-2 at 8 bit, but i can't run the simulation because i get this error:
[/CODE]
here are the two file code:
View attachment koggestone.vhd.txtView attachment koggestoneTB.vhd.txt
Thanks a lot in advance
ps here there is the schematic at 16bit that i followed!
i'm back again with a new error!!!
i wrote the vhdl code of a kogge-stone radix-2 at 8 bit, but i can't run the simulation because i get this error:
Code:
[CODE]# vsim -voptargs=+acc work.ks_tb
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading work.ks_tb(tb)
# Loading work.ks(arcks)
# Loading work.redblock(arcred)
# Loading work.yellowblock(arcyellow)
# Loading work.blueblock(arcblue)
# ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf
# File in use by: Hostname: ProcessID: 1
# Attempting to use alternate WLF file "./wlftc4my1s".
# ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf
# Using alternate file: ./wlftc4my1s
# ** Warning: (vsim-8683) Uninitialized out port /ks_tb/uut/s9(8 downto 0) has no driver.
# This port will contribute value (UUUUUUUUU) to the signal network.
# Region: /ks_tbhere are the two file code:
View attachment koggestone.vhd.txtView attachment koggestoneTB.vhd.txt
Thanks a lot in advance
ps here there is the schematic at 16bit that i followed!