Dec 6, 2011 #1 D dk614nd Advanced Member level 4 Joined Aug 8, 2006 Messages 106 Helped 46 Reputation 92 Reaction score 17 Trophy points 1,298 Activity points 1,997 Hi, I need pdf or ppt or link which explains the SSTL termination used for DDR1, DDR2 and DDR3 regards
Hi, I need pdf or ppt or link which explains the SSTL termination used for DDR1, DDR2 and DDR3 regards
Dec 7, 2011 #2 cks3976 Full Member level 6 Joined Aug 8, 2007 Messages 344 Helped 84 Reputation 168 Reaction score 81 Trophy points 1,308 Location India Activity points 3,324 Register on JEDEC to download the standard documents : STUB SERIES TERMINATED LOGIC FOR 1.8 V (SSTL_18): | JEDEC ---------- Post added at 07:14 ---------- Previous post was at 06:54 ---------- Some more links : https://www.edaboard.com/threads/130370/ SSTL Interface Description, Stub Series Terminated Logic for DDR, DDR2, DDR3 Electrical layer, SSTL-2, SSTL-18, SSTL-3 http://www.ece.unh.edu/courses/ece711/refrense_material/hs_memory/sstl_2spec.pdf : An old standard, but useful reading http://www.ti.com/lit/an/scba014/scba014.pdf
Register on JEDEC to download the standard documents : STUB SERIES TERMINATED LOGIC FOR 1.8 V (SSTL_18): | JEDEC ---------- Post added at 07:14 ---------- Previous post was at 06:54 ---------- Some more links : https://www.edaboard.com/threads/130370/ SSTL Interface Description, Stub Series Terminated Logic for DDR, DDR2, DDR3 Electrical layer, SSTL-2, SSTL-18, SSTL-3 http://www.ece.unh.edu/courses/ece711/refrense_material/hs_memory/sstl_2spec.pdf : An old standard, but useful reading http://www.ti.com/lit/an/scba014/scba014.pdf