msdarvishi
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Hello everyone,
I designed a Time-to-Digital Converter (TDC) configured by CARRY4 primitive in Virtex-5 (XC5VLX50T) FPGA using ISE 14.7 and Isim as the simulatior for Post place and route simulation purpose.
As you see, in the attached figure, my "clk_in" signal is 200 MHz fed to the DCM and the "output_test_point" is the output 2X of DCM that provides 400MHz clock signal for my TDC. I configured a delay line with 64 stages of CARRY4 resulting in 256 output bits. As you see, the "latched_output(255:0)" is the output of my TDC passed through D-flipflops to be sampled (each output of 256 bits passes through a Dflipflop). I am very surprised why the "latched_output" signal has undefined values 'X' at some signals?
It seems that the 'X' signals have different drivers, but I do not know how to recongize it?? Is there any way in Isim to find out the corresponding driver schematic for each signal after post place and route simulation?
I would cordially apprciate any help from you to solve this bug !
Thanks,
I designed a Time-to-Digital Converter (TDC) configured by CARRY4 primitive in Virtex-5 (XC5VLX50T) FPGA using ISE 14.7 and Isim as the simulatior for Post place and route simulation purpose.
As you see, in the attached figure, my "clk_in" signal is 200 MHz fed to the DCM and the "output_test_point" is the output 2X of DCM that provides 400MHz clock signal for my TDC. I configured a delay line with 64 stages of CARRY4 resulting in 256 output bits. As you see, the "latched_output(255:0)" is the output of my TDC passed through D-flipflops to be sampled (each output of 256 bits passes through a Dflipflop). I am very surprised why the "latched_output" signal has undefined values 'X' at some signals?
It seems that the 'X' signals have different drivers, but I do not know how to recongize it?? Is there any way in Isim to find out the corresponding driver schematic for each signal after post place and route simulation?
I would cordially apprciate any help from you to solve this bug !
Thanks,
