Uncertainty for variation

[srshankar]

Hi,

How is Uncertainty being used when considering on chip variations?? Could somebody please elaborate ..
Pls let me know how are variations taken care before 'derates' concept.

 

[hsyoo125]

Timing derate does not take effect on clock uncertainty. (At least, for STA)

You may regard clock uncertainty as additional timing margin.

 

[srshankar]

Timing derate does not take effect on clock uncertainty. (At least, for STA)

You may regard clock uncertainty as additional timing margin.

But why are we going for derates while 'uncertainty' margin is still applying ?? any limitations to 'uncertainty' ??

 

[ro9ty]

Uncertainty is that extra margin we apply for unexpected but possible delays. Your question is valid because if we have uncertainty then what is the need. But let us take a scenario. A design is not so critical about timing. You do not have to specify derate but just an uncertainty of 200ps would be sufficient. Well and fine.
But then you have a project that is highly timing critical. It has long non-common paths which are very much prone to OCV effect. In this case just mentioning an uncertainty will not be accurate. It would be a vague assumption. Hence, to make it mathematically more reliable, such that delay of the cells is efectively computed we will apply derate factors.
This derate factor will increase the delay in late paths and reduce delayin min paths (data and clock respectively in case of setup) thus creating a more valid computation.
Let us say you specified an uncertainty of 200ps.. Now for a path with 2 cells or 200cells it would be same but if you have derate factors it won't be same. It will increase delay for 200.

Ro9ty

- - - Updated - - -

Usually, OCV is only considering the process variations (sometimes voltage too) but the variations due to temperature or clock jitter etc.. cannot be estimated using derating factor. Hence you need to add uncertainty to adjust these delays.

 

[pdude]

Usually people say uncertainty = clock skew+jitter (before CTS)
= only jitter (after CTS) Why so?

 

[rahul.achates]

After synthesis , there is no information about the routing delay and hence clock tree information were not there. To take this delay in account, We declare clock uncertainty which will take care for clock skew + jitter.

During STA, we have information about clocks network and while calculating timing path, tool will calculate the clock delay along with data delay. the only thing need to take care in STA is jitter , that'why we give uncertainty for jitter in sta.

Rahul