Mar 5, 2010 #1 S sandy.vb Newbie level 5 Joined Mar 3, 2010 Messages 8 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Location India Activity points 1,339 hello i wanted to know how to carry out a unary OR operation on the bits of an array in VHDL, the verilog analog for which is as follows : (|reg_1[31:0]), where reg_1 is a register of appropriate size. thanks in advance.
hello i wanted to know how to carry out a unary OR operation on the bits of an array in VHDL, the verilog analog for which is as follows : (|reg_1[31:0]), where reg_1 is a register of appropriate size. thanks in advance.
Mar 6, 2010 #2 T TA37 Member level 3 Joined Feb 5, 2010 Messages 57 Helped 8 Reputation 16 Reaction score 5 Trophy points 1,288 Activity points 1,734 or_reduce(vector) You can either quickly code your own, see page 6 of **broken link removed** for an example, or try using the IEEE reduce_Pack package **broken link removed** ....or it looks like IEEE.std_logic_misc package has it too. http://cs.umbc.edu/~squire/download/std_logic_misc.vhdl
or_reduce(vector) You can either quickly code your own, see page 6 of **broken link removed** for an example, or try using the IEEE reduce_Pack package **broken link removed** ....or it looks like IEEE.std_logic_misc package has it too. http://cs.umbc.edu/~squire/download/std_logic_misc.vhdl