Re: Unable to understand timing diagram of a digital ckt
OK... then for the first diagram, at the rising edge of the clock, since the input was low (due to delay in change of input), the output was logic zero and so on. For the second diagram, the output changed as per the input during the rising edge of the clock after the tcpq delay (delay between clock edge arrival and output q arrival). Hope this explanation of the diagrams is correct. And yes, thanks for your patience.
Hobbyiclearner