One common problem occurs when there is a continuous read in the HDL code, as
shown in the following examples. You should avoid using these coding styles:
Code:
//Verilog HDL concurrent signal assignment
assign q = ram[raddr_reg];
-- VHDL concurrent signal assignment
q <= ram(raddr_reg);
When a write operation occurs, this type of HDL implies that the read should
immediately reflect the new data at the address, independent of the read clock.
However, that is not the behavior of TriMatrix memory blocks. In the device
architecture, the new data is not available until the next edge of the read clock.