Is there anyone who's used UMC 28nm for analog circuit before?
In this process, the POLY high density checking window is 1mmX1mm stepping 500um, is that possible? It's a big question mark.
This I believe is only a crude rules-check window to
ensure that alignable pattern exists no matter where
the machine "looks". The step can be as crude as the
size of the aligner field-of-view (or maybe half, just to
be safe).
Scanning the database at 500nm, X times Y, would be
a huge and unwelcome amount of crunch-time.
This I believe is only a crude rules-check window to
ensure that alignable pattern exists no matter where
the machine "looks". The step can be as crude as the
size of the aligner field-of-view (or maybe half, just to
be safe).
Scanning the database at 500nm, X times Y, would be
a huge and unwelcome amount of crunch-time.
Thanks for the explaination. Unfortunately, we didn't find other rules for high poly density checking in this process than this rule.
Do you mean that we can't rely on this rule for doing the high poly density checking?
I don't think the window matters, within each window
"step" there ought to be a density check done and
all must pass. Might inspect the next layer of this,
within the window what density criterion is called
out and does this criterion match what you see or
expect?
I don't think the window matters, within each window
"step" there ought to be a density check done and
all must pass. Might inspect the next layer of this,
within the window what density criterion is called
out and does this criterion match what you see or
expect?
window matters because of IP density versus chip density. that is the summary.
but reality is that it is so much more complicated than that in advanced technologies. poly is gridded, regular, and always occuring. you actually draw poly cuts for places where you don't want poly.