Hi,
I think it is not impossible. Here is a thesis that is based on ultra low power SRAM design:
https://dspace.mit.edu/handle/1721.1/53305 In that study main idea was first reducing leakage currents which consequently makes possible for designing with very low supply voltages (~0.3V). Another study that I saw was named as "A low-power SRAM design using quiet-bitline architecture" which can be found in IEEE Xplore, they have obtained 1.3-1.5 mA current rates for a 2kb SRAMs. So I think your assumption 20mA is too high when compared to these designs.