Your post sounds really confused. According to the datasheet, the busy signal doesn't help you in determining the correct
timing for read data.
Your considerations about receive time margin are very unclear. Typically, the serial data is sampled on the falling clock edge.
Clearly you have to count data bits correctly related to conversion start. As the clock is continuously running, you can also read
the data continuously to the DATA A/B shift registers. You have to determine the correct cycle, when to latch the shift register to
the parallel data output, that's all.
The timing specification suggests, that a new conversion can be started on each 16th clock cycle, which leads to a simple timing scheme.